JOB ID 28213
Semiconductor Principal Design Engineer
- メーカー, 半導体
- 半導体, 研究・開発
- 広島県
- 800万円～2000万円
This company is a global leader in semiconductor memory, specializing in the research, development, manufacturing, and sale of advanced memory technologies used in a wide range of products such as smartphones, data centers, automotive systems, and industrial applications. With a strong focus on innovation and engineering excellence, the organization plays a critical role in enabling technologies like artificial intelligence, cloud computing, and the Internet of Things. It operates within a highly collaborative and international environment, combining cutting-edge technical expertise with a strong emphasis on operational efficiency and talent development. The company is also known for fostering a performance-driven culture while maintaining a supportive workplace that values continuous learning, diversity, and employee growth.
As a Principal Design Engineer within Micron’s NAND Engineering Group (NVEG), you will lead the design and optimization of advanced datapath architectures for next-generation 3D NAND memory products. You will be responsible for developing high-speed, low-power TSV (Through-Silicon Via) interface circuits and highly parallel internal bus architectures that enable improved performance, signal integrity, and power efficiency. Working closely with circuit design, process technology, DTCO, packaging, and product engineering teams, you will drive key architectural decisions and guide projects from concept through silicon validation. In this role, you will perform timing, signal integrity, and power integrity analysis while ensuring robust design-for-testability and redundancy implementation across complex memory subsystems. You will also support silicon bring-up, debug, and yield improvement activities, identifying opportunities to enhance product quality and manufacturability. Through technical leadership and cross-functional collaboration, you will help shape future NAND memory technologies that support AI, cloud, and high-performance computing applications.
募集要項
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- 職種要約
- - Lead the architecture, design, and optimization of advanced datapath circuits for next-generation 3D NAND memory products.
- Design and validate TSV (Through-Silicon Via) interface circuits, including high-speed Rx/Tx paths, timing analysis, and impedance optimization.
- Develop highly parallel internal bus architectures with a focus on signal integrity, power efficiency, clock distribution, and timing closure.
- Define and implement design-for-testability (DFT), redundancy, and lane repair schemes to improve product quality, reliability, and manufacturability.
- Collaborate with process technology, DTCO, packaging, and product engineering teams to optimize memory architectures and resolve complex technical challenges.
- Support silicon bring-up, validation, debugging, and yield improvement activities by driving root cause analysis and corrective actions.
- Lead cross-functional design projects, communicate technical trade-offs to stakeholders, and drive the adoption of advanced design methodologies and AI-enabled workflows.
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- 応募資格（必須）
- - BS or MS in Electrical Engineering.
- 8+ years of experience in memory circuit design, preferably within NAND, DRAM, or other high-density memory technologies.
- Proven experience leading complex circuit design projects across multiple functional teams.
- Strong background in TSV (Through-Silicon Via) interface design or high-speed memory interfaces such as LPDDR4/5/6, DDR4/5, NV-LPDDR4, or HBM3/HBM4.
- Deep understanding of timing analysis, parasitic modeling, signal integrity, power integrity, and high-speed I/O design.
- Experience designing and optimizing highly parallel datapath architectures, including clock distribution, skew management, and timing closure.
- Experience with functional verification, circuit simulation, and silicon validation/debug.
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- 応募資格（優遇）
- - Hands-on experience applying AI tools to improve design quality, productivity, and engineering workflows.
- Knowledge of chip-level power delivery network (PDN) optimization.
- Strong understanding of CMOS devices, BSIM models, device reliability, and high-speed I/O requirements.
- Experience with signal integrity (SI), power integrity (PI), physical design, and semiconductor packaging considerations.
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- 勤務地
- 広島県
-
- 勤務スタイル
- 在宅勤務OK, フレックス勤務OK
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- 給与
- 800万円～2000万円
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- こだわり条件
- 上場企業, 転勤なし, 外資系企業, 海外折衝, 語学を活かす, 土日祝休み
Consultation
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